*** Artificial Neural Network for Hardware Functional Verification - a Survey***
*** Artificial Neural Network for Stimulus Generation Optimization in Hardware Functional Verification***.
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Researches
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My research is about the application of Artificial Intelligence and Machine Learning to hardware verification with my current focus on Artificial Neural Networks.
At the moment I am going to write and publish some works in the following direction:
*** Artificial Neural Network for Hardware Functional Verification - a Survey***
*** Artificial Neural Network for Stimulus Generation Optimization in Hardware Functional Verification as a particular research and development project***.
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Development
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In addition to paper writing, I am also planning to develop some tools, codes, apps for use together with verification tools and environments, either as standalone, plugins or modules for EDA tools. As a eginning I will make some AI tools for
***Stimulus Generation Optimization in Hardware Functional Verification***,
and then more tools will be developed using AI techniques.
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Some Background
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My IC career has been undergoing a long path, telling the whole story is not the purpose of this introductory message. However, I can simply summarize them in the following:
I started designing ICs since 2013.
At first,I have been concentrated on design and verification of ICs and IP cores for wireless communications (modulation and demodulation) during 2018-2022, particularly for satellite broadband Internet.
On the other hand, I have been involving in AI well almost for the same time span as my IC career, since 2013, when I was studying the graph-theoretical aspects of IC (integrated circuits) design, where AI is also key to developing EDA algorithms for VLSI design. A couple of years ago my IC verification activities have also been involving lots of AI/ML techniques and algorithms, as well as my quantum circuits design for example qubit routing which employs deep reinforcement learning to improve the routing efficiency.
My current design focuses on hardware verification, particularly verification with UVM, OSVVM, UVVM, cocotb, ABV (SVA, PSL).
My current research activity in this area is the application of Artificial Intelligence and Machine Learning to hardware verification with my current focus on Neural Networks.
Authoring
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I used also to write the gigantic book series titled “Silicon IP – Not just Design”.
As far as authoring about verification technoogy is concerned, I have been authoring a huge volume of books containing all aspects of the verification processes - from methodologies to languages, from platforms to testing systems. My first book in this direction was related to verification languages with Python, and afterwards SystemC, VHDL, (System)Verilog and a bunch of other verification languages.;then come the verification methodologies - UVM, UVVM, OSVVM, OVM etc.
Books I have drafted include the following:
Protecting Your IP Cores
Review of Verification IP & IP Core Verification – An Abstract
Verification Methodologies - A Concise Introduction
Comprehensive Review of Hardware Verification Languages (Except Python)
Hardware Verification Planning - A Concise Introduction
Hardware Verification Planning Tools
Hardware Verification in Python |